So, yeah, the idea is to, I reread the abstract when you sent it around and there was like
this boring part about the project, so I tried to squeeze it a little bit so we got a little
bit more in the technical part, see if I can manage in the time.
So nevertheless, I have a couple of slides of introduction because I don't know the audience.
First of all, I have two parts of the introduction.
One is the introduction to RISC-V. I don't know, so how many in the room are familiar
with RISC-V or at least you know what it is.
Okay, okay, so I can be fast here.
And then another one related to the project.
So how do we see RISC-V?
So how many of you are old enough to have been traveling with this kind of connectors?
Right?
Okay, exactly.
So we've been with the Nokia plug and then the Siemens plug and now we have a universal
standard bus, right?
It's universal.
So all the companies involved in the connector adopted, here I have a disclaimer, I apologize
if you are still an Apple user, but anyhow at some point you will come and you will understand
that having a standard is a benefit for everybody, right?
Because I arrived here and they gave me a USB-C connector and everything was working,
right?
Almost.
So having standards is good.
So which relationship we do have between this funny slide and the RISC-V?
Well, the message that we would like, the first message that we want to deliver usually
when we introduce RISC-V is that we see it as a standard for instruction sets.
In fact, if you think about the history of computer architecture, there have always been
or almost always been instruction set as being proprietary, very common maybe, like Intel
in the last 20 years, but not really an open standard that anybody can pick up and make
a CPU out of it, say for free.
So the idea of RISC-V is exactly this.
So let's define well-defined instruction set architecture that actually is what is what
represented here.
The basic instruction are not so many, you can print it out in an A4 and have it in your
own room and define well the instruction set and let everybody use it.
And that's actually should be something that has no royalties behind it.
We just sit down and decide which are the instruction and then everything else, well,
you can make a business out of it.
If you do your own implementation, you can still sell it.
Another important thing is that probably with these instructions, you can just handle a
few of the operation.
Maybe you need, we are going to talk about vector extension.
So RISC-V is an incremental instruction set in the sense that you have different modules
that you can, sorry, a modular instruction set RISC-V versus incremental that is x86.
So we are going to talk about vectors.
Vector is one of the module of the extension that you can enable.
Here in this table is nice because in the last column you see how many instructions
you have in each extension.
There are extensions that are only a few instructions.
The hypervisor has only two instructions or the user level has three instructions.
Presenters
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01:15:11 Min
Aufnahmedatum
2024-12-20
Hochgeladen am
2024-12-20 11:16:04
Sprache
en-US
Speaker: Dr. Filippo Mantovani, Barcelona Supercomputing Center
Slides: Erlangen-RISC-V-seminar-PUBLIC.pdf
Abstract:
The European Processor Initiative (EPI) is a project dedicated to developing a general-purpose processor and an accelerator, alongside the necessary software layers for their integration into the High Performance Computing (HPC) ecosystem. The Barcelona Supercomputing Center is contributing to the development of a RISC-V-based accelerator targeted at HPC applications, leveraging the RISC-V vector extension. This talk aims to provide a comprehensive overview of the EPI project, an introduction to RISC-V, and insights into vector supercomputing. Special emphasis will be placed on the RISC-V vector extensions (RVV), with a particular focus on implementations utilizing large vectors. Participants will gain an understanding of how RVV compares with other vector architectures and explore a design approach that utilizes vectors up to 16-kbit wide. Ultimately, the talk aims to present the methodologies, tools, and libraries available for vectorization, while addressing the accompanying challenges and limitations.
Short bio:
Filippo Mantovani is an established researcher responsible for the Mobile and embedded-based HPC group at the Barcelona Supercomputing Center (BSC). He graduated in mathematics and holds a Ph.D. in Computer Science from the University of Ferrara, Italy. He has been a scientific associate at the DESY laboratory in Zeuthen, Germany, and the University of Regensburg, Germany, spending most of his scientific career in computational physics and high-performance computing. He brought up and evaluated large high-performance computing systems, contributing to the Janus, QPACE and Mont-Blanc projects. Furthermore, he is involved in the FPGA prototyping tasks of RISC-V-based accelerators within the European Processor Initiative (EPI). Also, he is currently leading the collaboration between BSC and industrial group Etxe-tar for optimizing high-throughput manufacturing systems.